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| 型號： | TMS470R1A384PZ-T |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 56/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RISC MCU 384K FLASH 100-LQFP |
| 標準包裝： | 90 |
| 系列： | TMS470 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 48MHz |
| 連通性： | CAN，C2Slb，I²C，SCI，SPI |
| 外圍設備： | DMA，PWM，WDT |
| 輸入/輸出數(shù)： | 53 |
| 程序存儲器容量： | 384KB（384K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.71 V ~ 2.05 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 718 (CN2011-ZH PDF) |
| 配用： | 296-23003-ND - KIT DEV KICKSTART TMS470 |
| 其它名稱： | 296-19292 |
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SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
The A384 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The
SPI provides a convenient method of serial interaction for high-speed communications between similar
shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication
between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a
serial, multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy
and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring.
The C2SIb allows the A384 to transmit and receive messages on a class II network following an SAE J1850(2)
standard. The I2C module is a multi-master communication module providing an interface between the A384
microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and
400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the
specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional
information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number
SPNU223). For more detailed functional information on the C2SI, see the TMS470R1x Class II Serial Interface B
(C2SIb) Reference Guide (literature number SPNU214).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For
more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide
(literature number SPNU199).
The A384 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The A384 device has one 10-bit-resolution sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A384 device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).
NOTE:
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The expansion bus module (EBM) is a stand-alone module that supports the multiplexing of the GIO functions
and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module
(EBM) Reference Guide (literature number SPNU222).
The A384 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
(2)
SAE Standard J1850 Class B Data Communication Network Interface.
6
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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| TMS470R1A384PZ-TR | 制造商:Texas Instruments 功能描述:48MHZ / 384K FLASH - Tape and Reel |
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