參數(shù)資料
型號: TMS470R1A384PZ-T
廠商: Texas Instruments
文件頁數(shù): 41/62頁
文件大?。?/td> 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標準包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
其它名稱: 296-19292
SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode
(1) (2) (3)
Data Valid
SCICLK
SCITX
SCIRX
tc(SCC)
tw(SCCL)
tw(SCCH)
td(SCCH TXV)
tv(TX)
tsu(RX SCCL)
tv(SCCL RX)
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
(BAUD + 1)
IS EVEN OR BAUD = 0
IS ODD AND BAUD
≠ 0
UNIT
MIN
MAX
MIN
MAX
Cycle time,
tc(SCC)
2tc(ICLK)
224 tc(ICLK)
3tc(ICLK)
(224 -1) tc(ICLK)
ns
SCInCLK
Pulse duration,
tw(SCCL)
0.5tc(SCC) - tf
0.5tc(SCC) + 5
0.5tc(SCC) + 0.5tc(ICLK) - tf
0.5tc(SCC) + 0.5tc(ICLK)
ns
SCInCLK low
Pulse duration,
tw(SCCH)
0.5tc(SCC) - tr
0.5tc(SCC) + 5
0.5tc(SCC) - 0.5tc(ICLK) - tr
0.5tc(SCC) - 0.5tc(ICLK)
ns
SCInCLK high
Delay time,
td(SCCH-TXV)
SCInCLK high to
10
ns
SCInTX valid
Valid time,
SCInTX data
tv(TX)
tc(SCC) - 10
ns
after SCInCLK
low
Setup time,
tsu(RX-SCCL)
SCInRX before
tc(ICLK) + tf + 20
ns
SCInCLK low
Valid time,
SCInRX data
tv(SCCL-RX)
-tc(ICLK) + tf + 20
- tc(ICLK) + tf + 20
ns
after SCInCLK
low
(1)
BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
(2)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
A.
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
46
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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