參數(shù)資料
型號: TMS417400P
廠商: Texas Instruments, Inc.
英文描述: 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
中文描述: 4194304 - Word的4位高速DRAM等
文件頁數(shù): 4/30頁
文件大?。?/td> 441K
代理商: TMS417400P
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
test mode
The test mode is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode
if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits
×
4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin separately. If the four bits agree, DQ goes high; if not, DQ goes low. During
a write cycle, the data states of all four DQs must be the same to ensure proper function of the test mode. Test
time is reduced by a factor of four for this series.
Test Mode Cycle
Entry Cycle
Exit Cycle
Normal
Mode
RAS
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
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