參數(shù)資料
型號: TMS417400P
廠商: Texas Instruments, Inc.
英文描述: 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
中文描述: 4194304 - Word的4位高速DRAM等
文件頁數(shù): 13/30頁
文件大?。?/td> 441K
代理商: TMS417400P
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4xx400-60
’4xx400P-60
’4xx400-70
’4xx400P-70
’4xx400-80
’4xx400P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
tWC
tRWC
tPC
tPRWC
tRASP
tRAS
tCAS
tCP
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWRP
tWTS
tCAH
tDH
tRAH
tRCH
tRRH
tWCH
tRHCP
tOEH
tROH
tCHS
tWRH
tWTH
NOTES:
Cycle time, read (see Note 6)
110
130
150
ns
Cycle time, write (see Note 6)
110
130
150
ns
Cycle time, read-write (see Note 6)
155
181
205
ns
Cycle time, page-mode read or write (see Notes 6 and 7)
40
45
50
ns
Cycle time, page-mode read-write (see Note 6)
85
96
105
ns
Pulse duration, RAS low, page mode (see Note 8)
60
100 000
70
100 000
80
100 000
ns
Pulse duration, RAS low, nonpage mode (see Note 8)
60
10 000
70
10 000
80
10 000
ns
Pulse duration, CAS low (see Note 9)
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data (see Note 10)
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Setup time, W low before RAS low (test mode only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
Hold time, data (see Note 10)
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, W high after CAS high (see Note 11)
0
0
0
ns
Hold time, W high after RAS high (see Note 11)
0
0
0
ns
Hold time, W low after CAS low (early-write operation only)
10
15
15
ns
Hold time, RAS high from CAS precharge
35
40
45
ns
Hold time, OE command
15
18
20
ns
Hold time, RAS referenced to OE
10
10
10
ns
Hold time, CAS low after RAS high (self refresh)
– 50
– 50
– 50
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
Hold time, W low after RAS low (test mode only)
10
10
10
ns
6. All cycle times assume tT = 5 ns.
7. To assure tPC min, tASC should be
to tCP.
8. In a read-write cycle, tRWD and tRWL must be observed.
9. In a read-write cycle, tCWD and tCWL must be observed.
10. Referenced to the later of CAS or W in write operations
11. Either tRRH or tRCH must be satisfied for a read cycle.
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