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參數(shù)資料
| 型號(hào)： | TMS370 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | RADIO FREQUENCY I DENTIFICATION SYSTEMS |
| 中文描述： | 射頻我擠密系統(tǒng) |
| 文件頁數(shù)： | 30/54頁 |
| 文件大?。?/td> | 785K |
| 代理商： | TMS370 |
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TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
The ADIN register shows the data present at the pins configured for general-purpose input instead of ADC3
channels. A bit is configured as general-purpose input if the corresponding bit of the port-enable register
is a 1. Pins configured as ADC3 channels are read as 0’s. Writing to this address has no effect.
Table 19. AN0–AN7 Input-Enable Register
(ADENA)
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áá
P07E
Bit #
á
7
á
6
áá
5
á
4
á
3
áá
2
á
1
á
0
á
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ááá
INPUT
INPUT
á
ááá
INPUT
ááá
INPUT
INPUT
á
ááá
INPUT
ááá
INPUT
ááá
INPUT
The ADENA register individually configures the pins AN0–AN7 as either analog input channels
or as general-purpose input pins
0 = The pin becomes an analog-input channel for the ADC3. When the bit is 0, the
corresponding bit in the ADIN register reads a 0.
1 = Enables the pin as a general-purpose input pin and its digital value can be read from the
corresponding bit in the ADIN register.
Table 20. Analog Interrupt Priority/Conversion Rate Register
(ADPRI)
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R = read, W = write, P = privileged write, –n= value of the bit after the register is reset
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Bit #
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P07F
7
6
5
4
—
3
—
2
1
0
AD
AD
AD
—
AD RATE
AD RATE
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BIT 0–1
AD RATE SELECT 0–1 (ADC3 Conversion Rate Select Bits 0–1)
These bits determine the conversion rate of the ADC3 as a function of the system-clock frequency. Note that
only the default selection (0,0) provides full XTAL2/CLKIN frequency range together with 8-bit precision. Other
selections allow maintaining minimum conversion time at lower system-clock rates.
AD RATE
SELECT 1
AD RATE
SELECT 0
CONVERSION TIME
(NUMBER OF SYSTEM CLOCK CYCLES)
MAXIMUM SYSCLK
FREQUENCY
0
0
1
1
0
1
0
1
164
84
44
22
5 MHz
≥
SYSCLK > 2.5 MHz
2.5 MHz
≥
SYSCLK > 1.25 MHz
1.25 MHz
≥
SYSCLK > 0.625 MHz
0.625 MHz
≥
SYSCLK
≥
0.5 MHz
NOTE: If selections different from (0,0) are used at XTAL2/CLKIN frequencies higher than specified in this table, the
8-bit precision of the ADC3 is not assured.
BIT 2–4
RESERVED (Read data is indeterminate)
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