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參數(shù)資料
| 型號(hào)： | TMS370 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | RADIO FREQUENCY I DENTIFICATION SYSTEMS |
| 中文描述： | 射頻我擠密系統(tǒng) |
| 文件頁數(shù)： | 11/54頁 |
| 文件大小： | 785K |
| 代理商： | TMS370 |
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TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
program EPROM
The TMS370C792 contains 8K bytes of program EPROM memory mapped beginning at location 6000h and
continuing through location 7FFFh as shown in Figure 3. Memory addresses 7FE0h through 7FEBh are
reserved for Texas Instruments (TI
) and addresses 7FECh through 7FFFh are reserved for interrupt and reset
vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h
and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During
programming, the EPROM is controlled by the program EPROM control register (EPCTL). The program
EPROM modules’ features include:
Programming
–
In-circuit programming capability if V
PP
is applied to the MC pin
Control register: Program EPROM programming is controlled by the program EPROM control registers
EPCTL located at the addresses in PF frame 1 as shown in Table 5.
–
Write protection: Writes to the program EPROM are disabled under the following conditions:
–
Reset: All programming to the EPROM module is halted.
–
Low-power modes
–
13 V not applied to MC
program ROM
The program ROM consists of 4K bytes of mask-programmable ROM. The program ROM is used for permanent
storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication.
Memory addresses 7FE0h through 7FEBh are reserved for TI and addresses 7FECh through 7FFFh are
reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are
located between addresses 7FC0h and 7FDFh.
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx9x CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
internally generated, while one (RESET) is controlled externally. These actions are as follows:
Externa
l
RESET pin. A low level signal can trigger an external reset. To assure a reset, the external signal
should be held low for one SYSCLK cycle (it is possible, however, that a signal of less than one SYSCLK
could cause a reset). See the TMS370 User’s Guide(literature number SPNU127) or the TMS370 Family
Data Manual(SPNS014B) for more information.
Watchdog (WD) timer.
A watchdog-generated reset occurs if an improper value is written to the WD key
register or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 User’s
Guide(literature number SPNU127) or the TMS370 Family Data Manual(SPNS014B) for more information.
Oscillator reset.
Reset occurs when the oscillator operates outside of the recommended operating range.
See the TMS370 User’s Guide(literature number SPNU127) or the TMS370 Family Data Manual
(SPNS014B) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x9x device to reset external system components. Additionally, if a cold start condition
(V
CC
is off for several hundred milliseconds), oscillator failure occurs, or RESET pin is held low, then the reset
logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag
(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 6 depicts the reset sources.
TI is a trademark of Texas Instruments Incorporated.
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