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參數(shù)資料
| 型號： | TMS3705A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | RADIO FREQUENCY I DENTIFICATION SYSTEMS |
| 中文描述： | 射頻我擠密系統(tǒng) |
| 文件頁數(shù)： | 31/54頁 |
| 文件大小： | 785K |
| 代理商： | TMS3705A |
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TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
BIT 5
AD ESPEN (Emulator Suspend Enable)
Normally this bit has no effect. However, when using the XDS emulator to debug a program, this
bit determines what happens to the ADC3 when the program is suspended by an action such as
a hardware or software breakpoint.
0 = When the emulator is suspended, the ADC3 continues to run until the conversion is
complete.
1 = When the emulator is suspended, the ADC3 is frozen so that its state can be examined at
the point that the emulator was suspended. The conversion data is indeterminate upon
restart.
BIT 6
AD PRIORITY (ADC3 interrupt priority select)
This bit selects the priority level of the ADC3 interrupt.
0 = ADC3 Interrupt is a higher priority (level 1) request.
1 = ADC3 Interrupt is a lower priority (level 2) request.
BIT 7
AD STEST (This bit must be cleared to ensure proper operation)
instruction set overview
Table 21 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the
‘370Cx9x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the
opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction
of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.
For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes
in eight SYSCLK cycles.
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