參數(shù)資料
型號： TMS3705A
廠商： Texas Instruments, Inc.
英文描述： RADIO FREQUENCY I DENTIFICATION SYSTEMS
中文描述： 射頻我擠密系統(tǒng)
文件頁數(shù)： 29/54頁
文件大小： 785K
代理商： TMS3705A
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
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AD INT ENA (ADC3 Interrupt Enable)
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BIT 0
AD
READY
AD INT
FLAG
AD INT
ENA
This bit controls the ADC3 module’s ability to generate an interrupt.
0 = Disable ADC3 interrupt.
1 = Enable ADC3 interrupt.
BIT 1
AD INT FLAG (ADC3 Interrupt Flag)
The ADC3 module sets this bit at the end of an A/D conversion. If this bit is set while the AD INT
ENA bit is set, an interrupt request is generated. Clearing this flag clears pending ADC3 interrupt
requests. This bit is cleared by the system reset or by entering HALT or STANDBY mode. Software
cannot set this bit.
BIT 2
AD READY (ADC3 Converter Ready)
The ADC3 module sets this bit whenever a conversion is not in progress and the ADC3 is ready
for a new conversion to start. Writing to this bit has no effect on its state.
0 = Conversion in process.
1 = Converter ready.
BIT 3–7
Reserved (Read data is indeterminate)
Table 17. ADC3
Conversion Data Register
(DATA)
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The analog-to-digital conversion data is loaded into this register at the end of a conversion and remains until
replaced by another conversion
Bit #
7
P072
DATA 7
6
R–0
5
R–0
R–0
4
3
R–0
2
R–0
1
R–0
0
R–0
R–0
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
R = read, –n= value of the bit after the register is reset
Table 18. AN0–AN7 Data Input Register
(ADIN)
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Bit #
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7
á
6
5
3
á
2
1
á
0
á
á
á
AN7
á
á
AN6
á
á
AN5
áá
R–0
4
á
AN3
á
á
AN2
á
AN1
R–0
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P07D
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R–0
PORT E
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ááá
R–0
PORT E
PORT E
DATA IN
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á
R–0
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AN4
PORT E
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ááá
R–0
PORT E
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ááá
R–0
PORT E
PORT E
DATA IN
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á
R–0
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ááá
AN0
PORT E
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