參數(shù)資料
型號： TMS32C6416DGLSA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 49/141頁
文件大?。?/td> 2234K
代理商： TMS32C6416DGLSA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
EMIFB (16-bit)
CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
||
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
BCE3
BCE2
BCE1
BCE0
A13
C12
B12
A12
EMIFB memory space enables
Enabled by bits 26 through 31 of the word address
Only one pin is asserted during any external data access
BBE1
D13
O/Z
IPU
EMIFB byte-enable control
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIFB peripheral data transfer, allows direct transfer between external peripherals
EMIFB (16-BIT)
BUS ARBITRATION
||
EMIFB hold-request-acknowledge to the host
EMIFB hold request from the host
EMIFB bus request output
EMIFB (16-BIT)
ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
||
EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.
BECLKIN is the default for the EMIFB input clock.
BBE0
C13
O/Z
IPU
BPDT
E12
O/Z
IPU
BHOLDA
BHOLD
BBUSREQ
E13
B19
E14
O
I
O
IPU
IPU
IPU
BECLKIN
A11
I
IPD
BECLKOUT2
D11
O/Z
IPD
EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided by 1, 2, or 4.
BECLKOUT1
D12
O/Z
IPD
EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
BARE/
BSDCAS/
BSADS/BSRE
A10
O/Z
IPU
EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between BSADS and BSRE:
If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal.
If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal.
BAOE/
BSDRAS/
BSOE
B11
O/Z
IPU
EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
BAWE/BSDWE/
BSWE
C11
O/Z
IPU
EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
BSOE3
BARDY
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
||
These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
E15
E11
O/Z
I
IPU
IPU
EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)
EMIFB asynchronous memory ready input
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