參數(shù)資料
型號: TMS32C6411ZLZA6E3
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 129/141頁
文件大?。?/td> 2234K
代理商: TMS32C6411ZLZA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146L
FEBRUARY 2001
REVISED JULY 2004
129
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED)
timing requirements for UTOPIA Slave receive (see Figure 60)
NO.
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
MAX
1
2
3
4
t
su(URDV-URCH)
t
h(URCH-URDV)
t
su(URAV-URCH)
t
h(URCH-URAV)
Setup time, URDATA valid before URCLK high
Hold time, URDATA valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
4
1
4
1
ns
ns
ns
ns
9
10
11
12
t
su(URENBL-URCH)
t
h(URCH-URENBL)
t
su(URSH-URCH)
t
h(URCH-URSH)
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
4
1
4
1
ns
ns
ns
ns
switching characteristics over recommended operating conditions for UTOPIA Slave receive
(see Figure 60)
NO.
PARAMETER
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
MAX
5
t
d(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value
3
12
ns
6
t
d(URCH-URCLAVL)
Delay time, URCLK high to URCLAV driven inactive low
3
12
ns
7
t
d(URCH-URCLAVHZ)
Delay time, URCLK high to URCLAV going Hi-Z
9
18.5
ns
8
t
w(URCLAVL-URCLAVHZ)
Pulse duration (low), URCLAV low to URCLAV Hi-Z
3
ns
P48
H1
H2
H3
N
0x1F
N+1
0x1F
N+2
0x1F
N
N+1
N+2
12
11
9
10
5
4
3
2
1
URCLK
URDATA[7:0]
URADDR[4:0]
URCLAV
URENB
URSOC
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
Figure 60. UTOPIA Slave Receive Timing
8
6
7
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