參數(shù)資料
型號： TMS32C6411AGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 69/119頁
文件大?。?/td> 1742K
代理商： TMS32C6411AGLZ
SPRS196H MARCH 2002 REVISED JULY 2004
69
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
Transmission Line
4.0 pF
1.85 pF
Z0 = 50
(see note)
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
42
3.5 nH
Device Pin
(see note)
Figure 12. Test Load Circuit for AC Timing Measurements
The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate
the maximum load the device is capable of driving.
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
IL
MAX and V
IH
MIN for input clocks, V
OL
MAX
and V
OH
MIN for output clocks, V
ILP
MAX and V
IHP
MIN for PCI input clocks, and V
OLP
MAX and V
OHP
MIN for
PCI output clocks.
Vref = VIL MAX (or VOL MAX or
VILP MAX or VOLP MAX)
Vref = VIH MIN (or VOH MIN or
VIHP MIN or VOHP MIN)
Figure 14. Rise and Fall Transition Time Voltage Reference Levels
signal transition rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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