- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382641 > TMS320LF2407PGS (Texas Instruments, Inc.) DSP CONTROLLERS PDF資料下載
參數(shù)資料
| 型號(hào)： | TMS320LF2407PGS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 54/115頁 |
| 文件大?。?/td> | 1511K |
| 代理商： | TMS320LF2407PGS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
external memory interface (LF2407)
The TMS320LF2407 can address up to 64K
×
16 words of memory (or registers) in each of the program, data,
and I/O spaces. On-chip memory, when enabled, occupies some of this off-chip range.
The CPU of the TMS320LF2407 schedules a program fetch, data read, and data write on the same machine
cycle. This is because from on-chip memory, the CPU can execute all three of these operations in the same
cycle. However, the external interface multiplexes the internal buses to one address bus and one data bus. The
external interface sequences these operations to complete first the data write, then the data read, and finally
the program read.
The LF2407 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces
provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address and data
buses, along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in program,
data, and I/O space. Since on-chip peripheral registers occupy positions of data-memory space (70007FFF),
the externally addressable data-memory space is 32K 16-bit words (8000FFFF). Note that the global memory
space of the C2xx core is not used for 240x DSP devices. Therefore, the global memory allocation register
(GREG) is reserved for all these devices.
Input/output (I/O) design is simplified by having I/O space treated the same way as memory. I/O devices are
accessed in the I/O address space using the processor’s external address and data buses in the same manner
as memory-mapped devices.
The LF2407 external parallel interface provides various control signals to facilitate interfacing to the device. The
R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles. For convenience, the device also provides the RD and the
WE output signals, which indicate a read cycle and a write cycle, respectively, along with timing information for
those cycles. The availability of these signals minimizes external gating necessary for interfacing external
devices to the LF2407.
The 2407 provides RD and W/R signals to help the zero-wait-state external memory interface. At higher
CLKOUT speeds, RD may not meet the slow memory device’s timing. In such instances, the W/R signal could
be used as an alternative signal with some tradeoffs. See the timings for details.
The TMS320LF2407 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the TMS320LF2407 to buffer the transition of the data bus from input to output
(or from output to input) by a half cycle. In most systems, the TMS320LF2407 ratio of reads to writes is
significantly large to minimize the overhead of the extra cycle on writes.
wait-state generation (LF2407 only)
Wait-state generation is incorporated in the LF2407 without any external hardware for interfacing the LF2407
with slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external
memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O
port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states
operate on CLKOUT cycle boundaries.
To avoid bus conflicts, writes from the LF2407 always take at least two CLKOUT cycles. The LF2407 offers two
options for generating wait states:
READY Signal. With the READY signal, you can externally generate any number of wait states. The READY
pin has no effect on accesses to
internal
memory.
On-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS320SP5410AGGU12 | Fixed-Point Digital Signal Processor |
| TMS320SP5410AZGU12 | Fixed-Point Digital Signal Processor |
| TMS32C6411ZLZA6E3 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMS32C6416EGLSA6E3 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMS32C6415CGLSA6E3 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320M640AGNZ4 | 制造商:Texas Instruments 功能描述:TMS320DM640 548PIN FCBGA PG2.0 - Trays |
| TMS320M641AGDK5 | 制造商:Texas Instruments 功能描述:TMS320DM641AGDK PG2 548 PIN FCBGA 500MHZ - Trays |
| TMS320M641AGDK6 | 制造商:Texas Instruments 功能描述:TMS320DM641AGDK PG2 548 PIN FCBGA - Trays |
| TMS320M641AGNZ5 | 制造商:Texas Instruments 功能描述:TMS320DM641A 548PIN FCBGA PG2.0 500MHZ - Trays |
| TMS320M641AGNZ6 | 制造商:Texas Instruments 功能描述:TMS320DM641A 548PIN FCBGA PG2.0 600 MHZ - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。