參數(shù)資料
型號: TMS320LF2402PGEA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP CONTROLLERS
中文描述: DSP控制器
文件頁數(shù): 16/115頁
文件大?。?/td> 1511K
代理商: TMS320LF2402PGEA
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240x Pin List and Package Options
(Continued)
PIN NAME
LF2407
LF2406
LF2402
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
D2
132
Bit 2 of 16-bit data bus
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D3
134
Bit 3 of 16-bit data bus
D4
136
Bit 4 of 16-bit data bus
D5
138
Bit 5 of 16-bit data bus
D6
143
Bit 6 of 16-bit data bus
D7
5
Bit 7 of 16-bit data bus
D8
9
Bit 8 of 16-bit data bus
D9
13
Bit 9 of 16-bit data bus
D10
15
Bit 10 of 16-bit data bus
D11
17
Bit 11 of 16-bit data bus
D12
20
Bit 12 of 16-bit data bus
D13
22
Bit 13 of 16-bit data bus
D14
24
Bit 14 of 16-bit data bus
D15
27
Bit 15 of 16-bit data bus
POWER SUPPLY
29
20
6
50
35
27
Core supply +3.3 V. Digital logic supply voltage.
VDD#
86
59
56
129
91
4
4
10
42
30
35
67
47
52
I/O buffer supply +3.3 V. Digital logic and buffer supply voltage.
VDDO#
77
54
95
64
141
98
28
19
5
49
34
26
Core ground. Digital logic ground reference.
VSS#
85
58
55
128
90
3
3
9
41
29
34
66
46
51
76
53
I/O buffer ground. Digital logic and buffer ground reference.
VSSO#
94
63
125
97
140
Bold, italicized pin names
indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
Internal pullup
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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