參數(shù)資料
型號： TMS320F2812GHHMEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 60/159頁
文件大小： 2084K
代理商： TMS320F2812GHHMEP
Peripherals
60
March 2004 Revised October 2004
SGUS051A
4.2.1
General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts:
underflow
,
overflow
,
timer compare
, and
period
interrupts
A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the
time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP
timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period
and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse
width as needed.
4.2.2
Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
4.2.3
Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit
output signal. The output states of the deadband generator are configurable and changeable as needed by
way of the double-buffered ACTRx register.
4.2.4
PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with
programmable deadbands
, and two
independent PWMs by the GP-timer compares.
4.2.5
Double Update PWM Mode
The F281x and C281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM
operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse
are independently modifiable in each PWM period. To support this mode, the compare register that determines
the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning
of a PWM period and another time in the middle of a PWM period. The compare registers in F281x and C281x
Event Managers are all buffered and support three compare value reload/update (value in buffer becoming
active) modes. These modes have earlier been documented as compare value reload conditions. The reload
condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR
Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for
compare value reload.
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