參數(shù)資料
型號： TMS320F2812GHHMEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 121/159頁
文件大?。?/td> 2084K
代理商： TMS320F2812GHHMEP
Electrical Specifications
120
March 2004 Revised October 2004
SGUS051A
6.22
External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 625 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 625. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)
X2TIMING = 0
XRDLEAD x tc(XTIM)
(XRDACTIVE + WS + 1) x tc(XTIM)
XRDTRAIL x tc(XTIM)
XWRLEAD x tc(XTIM)
(XWRACTIVE + WS + 1) x tc(XTIM)
XWRTRAIL x tc(XTIM)
X2TIMING = 1
(XRDLEAD x 2) x tc(XTIM)
(XRDACTIVE x 2 + WS + 1) x tc(XTIM)
(XRDTRAIL x 2) x tc(XTIM)
(XWRLEAD x 2) x tc(XTIM)
(XWRACTIVE x 2 + WS + 1) x tc(XTIM)
(XWRTRAIL x 2) x tc(XTIM)
LR
Lead period, read access
AR
Active period, read access
TR
Trail period, read access
LW
Lead period, write access
AW
Active period, write access
TW
tc(XTIM) Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Trail period, write access
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
If the XREADY signal is ignored (USEREADY = 0), then:
1.
Lead:
LR
≥
t
c(XTIM)
LW
≥
t
c(XTIM)
These requirements result in the following XTIMING register configuration restrictions
§
:
XRDLEAD
≥
1
§No hardware to detect illegal XTIMING configurations
XRDACTIVE
≥
0
XRDTRAIL
≥
0
XWRLEAD
≥
1
XWRACTIVE
≥
0
XWRTRAIL
≥
0
X2TIMING
0, 1
Examples of valid and invalid timing when not sampling XREADY
§
:
XRDLEAD
0
XRDACTIVE
0
XRDTRAIL
0
XWRLEAD
0
XWRACTIVE
0
XWRTRAIL
0
X2TIMING
0, 1
Invalid
Valid
§No hardware to detect illegal XTIMING configurations
1
0
0
1
0
0
0, 1
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