參數(shù)資料
型號(hào)： TMS320F2809_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 112/140頁
文件大?。?/td> 1108K
代理商： TMS320F2809_07
www.ti.com
t
d(IDLEXCOL)
X1/X2
or XCLKIN
XCLKOUT
HALT
HALT
Wake-up Latency
Flushing Pipeline
t
d(WAKEHALT)
(A)
(B)
(C)
(D)
Device
Status
(E)
(G)
(F)
PLL Lock-up Time
Normal
Execution
t
w(WAKE-GPIO)
t
p
GPIOn
Oscillator Start-up Time
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007
Table 6-21. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
cycles
cycles
t
d(IDLE-XCOL)
t
p
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
Delay time, PLL lock to program execution resume
Wake up from flash
–
Flash module in sleep state
32t
c(SCO)
45t
c(SCO)
131072t
c(OSCCLK)
1125t
c(SCO)
cycles
t
d(WAKE-HALT)
35t
c(SCO)
cycles
Wake up from SARAM
A.
B.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
Normal operation resumes.
C.
D.
E.
F.
G.
Figure 6-14. HALT Wake-Up Using GPIOn
112
Electrical Specifications
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