參數(shù)資料
型號(hào)： TMS320C6701GGP100
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 54/70頁(yè)
文件大小： 1050K
代理商： TMS320C6701GGP100
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP
(see Figure 33)
NO.
PARAMETER
200
UNIT
MIN
MAX
1
t
d(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
3
12
ns
2
3
4
t
c(CKRX)
t
w(CKRX)
t
d(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
2P
2
§
C
2
#
3
3
3
1
3
1
2
1
2
ns
ns
ns
C + 2
#
3
3
9
4
9
4
12
5
12
9
t
d(CKXH-FXV)
Delay time CLKX high to internal FSX valid
Delay time, CLKX high to internal FSX valid
ns
12
t
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
ns
13
t
d(CKXH-DXV)
Delay time CLKX high to DX valid
Delay time, CLKX high to DX valid
ns
14
t
d(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
#
C =
H or L
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
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