參數(shù)資料
型號： TMS320C6701GGP100
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 13/70頁
文件大?。?/td> 1050K
代理商： TMS320C6701GGP100
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
CLOCK/PLL
CLKIN
J3
I
Clock Input
Clock output at half of device speed
Used for synchronous memory interface
CLKOUT2
T19
O
CLKMODE0
L3
I
Clock mode select 0
Selects whether the on-chip PLL is used or bypassed. For more details, see the
Clock PLL
section.
The PLL Multiply Factor is selected at boot configuration. For more details, see the EMIF
Data
pin descriptions and the clock PLL section.
PLLV
PLLG
PLLF
K5
L2
L1
A
§
A
§
A
§
PLL analog V
CC
connection for the low-pass filter
PLL analog GND connection for the low-pass filter
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
JTAG test-port mode select (features an internal pullup)
JTAG test-port data out
JTAG test-port data in (features an internal pullup)
JTAG test-port clock
JTAG test-port reset (features an internal pulldown)
Emulation pin 1, pullup with a dedicated 20-k
resistor
Emulation pin 0, pullup with a dedicated 20-k
resistor
RESET AND INTERRUPTS
Device reset
Nonmaskable interrupt
Edge-driven (rising edge)
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
E17
D19
D18
D17
C19
E18
F15
I
O/Z
I
I
I
I/O/Z
I/O/Z
RESET
C3
I
NMI
A8
I
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
B15
C15
A16
B16
A15
F12
A14
B14
C14
I
External interrupts
d i
Edge-driven
Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL [3:0])
Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
O
Interrupt acknowledge for all active interrupts serviced by the CPU
O
Active interrupt identification number
V lid d i
IACK f ll
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
POWER-DOWN STATUS
PD
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the
clock PLL
section for information on how to connect these pins.
§
A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k
resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
B18
O
Power-down modes 2 or 3 (active if high)
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