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TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
Table 7-10. C6454 DSP Interrupts (continued)
EVENT NUMBER
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86 - 95
96
97
98
99
100
101
102 - 111
112
113
114 - 115
116
117
118
119
120
121
122
123
124
INTERRUPT EVENT
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
TINTLO0
TINTHI0
TINTLO1
TINTHI1
EDMA3CC_INT0
EDMA3CC_INT1
EDMA3CC_INT2
EDMA3CC_INT3
EDMA3CC_INT4
EDMA3CC_INT5
EDMA3CC_INT6
EDMA3CC_INT7
EDMA3CC_ERRINT
Reserved
EDMA3TC0_ERRINT
EDMA3TC1_ERRINT
EDMA3TC2_ERRINT
EDMA3TC3_ERRINT
Reserved
Reserved
INTERR
EMC_IDMAERR
Reserved
Reserved
EFIINTA
EFIINTB
Reserved
Reserved
L1P_ED1
Reserved
L2_ED1
L2_ED2
PDC_INT
Reserved
L1P_CMPA
L1P_DMPA
L1D_CMPA
L1D_DMPA
L2_CMPA
INTERRUPT SOURCE
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Timer 0 lower counter interrupt
Timer 0 higher counter interrupt
Timer 1 lower counter interrupt
Timer 1 higher counter interrupt
EDMA3CC completion interrupt - Mask0
EDMA3CC completion interrupt - Mask1
EDMA3CC completion interrupt - Mask2
EDMA3CC completion interrupt - Mask3
EDMA3CC completion interrupt - Mask4
EDMA3CC completion interrupt - Mask5
EDMA3CC completion interrupt - Mask6
EDMA3CC completion interrupt - Mask7
EDMA3CC error interrupt
Reserved. Do not use.
EDMA3TC0 error interrupt
EDMA3TC1 error interrupt
EDMA3TC2 error interrupt
EDMA3TC3 error interrupt
Reserved. Do not use.
Reserved. Do not use.
Interrupt Controller dropped CPU interrupt event
EMC invalid IDMA parameters
Reserved. Do not use.
Reserved. Do not use.
EFI interrupt from side A
EFI interrupt from side B
Reserved. Do not use.
Reserved. Do not use.
L1P single bit error detected during DMA read
Reserved. Do not use.
L2 single bit error detected
L2 two bit error detected
Powerdown sleep interrupt
Reserved. Do not use.
L1P CPU memory protection fault
L1P DMA memory protection fault
L1D CPU memory protection fault
L1D DMA memory protection fault
L2 CPU memory protection fault
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C64x+ Peripheral Information and Electrical Specifications
113