
TMS320AV120
MPEG AUDIO DECODER
SCSS014A – MARCH 1994 – REVISED JANUARY 1996
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reset sequence (continued)
tw3
tpd2
RESET
SREQ
Figure 5. Reset Timing
input processor
The input processor decodes the header and prepares the audio data for the arithmetic unit. If synchronization
is lost or an error is found in the header or during the CRC check (if the bit stream is protected), the PCM output
for that frame is muted. The status register is updated to signal a synchronization or CRC error.
PCM output interface
The decoded audio data is output in serial PCM-data format on PCMOUT. The data is output with the most
significant bit first. PCM data can be latched on the rising edge of the serial PCM output clock (SCLK). The data
output on PCMOUT alternates between the two channels as designated by LRCLK. If the input data stream is
monophonic, the same PCM data is output on both channels. As shown in Table 1, if the input data stream is
dual channel (two independent channels), the channel(s) output depends on the setting of OMODE.
Table 1. OMODE1 and OMODE0 Functional Summary
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OUTPUT
OUTPUT
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00
Channel 0
Channel 1
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The PCMSEL terminals select the ratio of PCMCLK to SCLK and the number of bits per PCM word. If the PCM
word size is 24, the first 6 bits are zeros followed by an 18-bit PCM value. Output precision and PCM word length
are selected by the PCMSEL terminals as shown in Table 2.
Table 2. PCMSEL1 and PCMSEL2 Functional Summary
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PCM
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