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| 型號： | TMS28F400BZT80BDBJL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES |
| 中文描述： | 8-BIT/262144由16位啟動塊閃存 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大小： | 404K |
| 代理商： | TMS28F400BZT80BDBJL |
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
byte-wide or word-wide mode selection (continued)
Table 4. Operation Modes for Word-Wide Mode (BYTE = V
IH
)
MODE
E
G
RP
W
A9
A0
VPP
X
DQ0–DQ15
Read
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
X
Data out
VID
VIL
X
Manufacturer-equivalent code 0089h
Algorithm-selection mode
VIL
VIL
VIH
VIH
VID
VIH
X
Device-equivalent code 4470h
(top boot block)
Device-equivalent code 4471h
(bottom boot block)
Output disable
VIL
VIH
X
VIH
X
VIH
VIH
VIL
VIH or
VHH
VIH
X
X
X
X
Hi-Z
Standby
X
X
X
Hi-Z
Reset/deep power down
X
X
X
X
X
Hi-Z
Write (see Note 1)
VIL
VIH
VIL
X
X
VPPL or
VPPH
Data in
X = Don’t care
NOTE 1: When writing commands to the ’28F400BZx, VPP must be VPPH for block-erase or program commands to be executed and RP must
be held at VHH for the entire boot-block program or erase operation.
Table 5. Operation Modes for Byte-Wide Mode (BYTE = V
IL
)
MODE
E
G
RP
W
A9
A0
VPP
X
DQ15/A–1
VIL
VIH
DQ8–DQ14
DQ0–DQ7
Read lower byte
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
X
Hi-Z
Data out
Read upper byte
X
X
X
Hi-Z
Data out
VIL
VIL
VIH
VIH
VID
VIL
X
X
Hi-Z
Manufacturer-equivalent
code 89h
Algorithm-selection
mode
Device-equivalent code
70h (top boot block)
VIL
VIL
VIH
VIH
VID
VIH
X
X
Hi Z
Hi-Z
Device-equivalent code
71h (bottom boot block)
Output disable
VIL
VIH
VIH
X
VIH
VIH
VIH
X
X
X
X
X
Hi-Z
Hi-Z
Standby
X
X
X
X
Hi-Z
Hi-Z
Reset/deep power
down
X
X
VIL
X
X
X
X
X
Hi-Z
Hi-Z
Write (see Note 1)
VIL
VIH
VIH or
VHH
VIL
X
X
VPPL
or
VPPH
X
Hi-Z
Data in
X = Don’t care
NOTE 1: When writing commands to the ’28F400BZx, VPP must be VPPH for block-erase or program commands to be executed and RP must
be held at VHH for the entire boot-block program or erase operation.
command state machine operations
The CSM decodes instructions for clear status-register, read array, read algorithm-selection code, read
status-register, program, erase, erase-suspend, and erase-resume operations. The 8-bit command code is
input to the device on DQ0–DQ7 (see Table 1 for CSM codes). During a program or erase cycle, the CSM
informs the WSM that a program or erase cycle has been requested. During a program cycle, the WSM controls
the program sequences and the CSM responds only to status reads.
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