參數(shù)資料
型號: TMS28F400BZT80BDBJL
廠商: Texas Instruments, Inc.
英文描述: 8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES
中文描述: 8-BIT/262144由16位啟動塊閃存
文件頁數(shù): 18/29頁
文件大?。?/td> 404K
代理商: TMS28F400BZT80BDBJL
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz, V
I
= 0 V
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ci
Co
Input capacitance
8
pF
Output capacitance
VO = 0 V
12
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
read operations
PARAMETER
ALT.
’28F400BZx80
’28F400BZx90
UNIT
SYMBOL
MIN
MAX
MIN
MAX
ta(A)
ta(E)
ta(G)
tc(R)
td(E)
td(G)
tdis(E)
tdis(G)
Access time from A0–A17 (see Note 10)
tAVQV
tELQV
tGLQV
tAVAV
tELQX
tGLQX
tEHQZ
tGHQZ
80
90
ns
Access time from E
80
90
ns
Access time from G
40
45
ns
Cycle time, read
80
90
ns
Delay time, E low to low-impedance output
0
0
ns
Delay time, G low to low-impedance output
0
0
ns
Disable time, E to high-impedance output
30
35
ns
Disable time, G to high-impedance output
30
35
ns
th(D)
Hold time, DQ valid from A0–A17, E, or G, whichever occurs first
(see Note 10)
tAXQX
0
0
ns
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
tPHQV
tFLQV
tFHQV
5
5
ns
td(RP)
tdis(BL)
ta(BH)
NOTE 10: A–1–A17 for byte-wide
Output delay time from RP high
300
300
ns
Disable time, BYTE low to DQ8–DQ15 in high-impedance state
30
35
ns
Access time from BYTE going high
80
90
ns
相關PDF資料
PDF描述
TMS28F400BZT90BDBJL 8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES
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