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參數(shù)資料
| 型號： | TMS28F400BZT80BDBJL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES |
| 中文描述： | 8-BIT/262144由16位啟動塊閃存 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 404K |
| 代理商： | TMS28F400BZT80BDBJL |
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reset/deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V
±
0.2 V, an I
CC
value on the order of 0.2
μ
A, or 1
μ
W
of power, is achievable. This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum
of t
d(RP)
is required before data is valid, and a minimum of t
rec(RPHE)
and/or t
rec(RPHW)
in deep power-down
mode is required before data input to the CSM can be recognized. With RP at ground, the WSM is reset and
the status register is cleared, effectively eliminating accidental programming to the array during system reset.
After restoration of power, the device does not recognize any operation command until RP is returned to a V
IH
or V
HH
level.
Should RP go low during a program or erase operation, the device will power down and, therefore, will become
nonfunctional and data being written or erased will be invalid or indeterminate, requiring that the operation be
performed again after power restoration.
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