
SPRS196H MARCH 2002 REVISED JULY 2004
71
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN
§
(see Figure 16)
300
NO.
PLL MODE x6
MIN
x1 (BYPASS)
MIN
UNIT
MAX
MAX
1
tc(CLKIN)
tw(CLKINH)
tw(CLKINL)
tt(CLKIN)
tJ(CLKIN)
Cycle time, CLKIN
20
33.3
13.3
33.3
ns
2
Pulse duration, CLKIN high
0.4C
0.45C
ns
3
Pulse duration, CLKIN low
0.4C
0.45C
ns
4
Transition time, CLKIN
5
1
ns
5
Period jitter, CLKIN
0.02C
0.02C
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factor (x6), see the
Clock PLL
section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
2
3
4
4
5
1
Figure 16. CLKIN Timing