參數(shù)資料
型號： TMP32C6411AZLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 43/119頁
文件大?。?/td> 1742K
代理商： TMP32C6411AZLZ
SPRS196H MARCH 2002 REVISED JULY 2004
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
IPU
DESCRIPTION
NAME
NO.
EMIF (32-bit) DATA§ (CONTINUED)
ED13
A20
ED12
D20
ED11
B20
ED10
C20
ED9
A21
ED8
D21
ED7
B21
I/O/Z
IPU
EMIF external data
ED6
C21
ED5
A22
ED4
C22
ED3
B22
ED2
B23
ED1
A23
ED0
A24
TIMER 2
TOUT2
A4
O/Z
IPD
Timer 2 or general-purpose output
TINP2
C5
I
IPD
Timer 2 or general-purpose input
TIMER 1
TOUT1
B5
O/Z
IPD
Timer 1 or general-purpose output
TINP1
A5
I
IPD
Timer 1 or general-purpose input
TIMER 0
TOUT0
D6
O/Z
IPD
Timer 0 or general-purpose output
TINP0
C6
I
IPD
Timer 0 or general-purpose input
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
AC8
I
McBSP1 external clock source (as opposed to internal)
CLKR1
AC10
I/O/Z
McBSP1 receive clock
CLKX1
AB12
I/O/Z
McBSP1 transmit clock
DR1
AF11
I
McBSP1 receive data
DX1
AB11
O/Z
McBSP1 transmit data
FSR1
AC9
I/O/Z
McBSP1 receive frame sync
FSX1
AB13
I/O/Z
McBSP1 transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
F4
I
IPD
McBSP0 external clock source (as opposed to internal)
CLKR0
D1
I/O/Z
IPD
McBSP0 receive clock
CLKX0
E1
I/O/Z
IPD
McBSP0 transmit clock
DR0
D2
I
IPU
McBSP0 receive data
DX0
E2
O/Z
IPU
McBSP0 transmit data
FSR0
C1
I/O/Z
IPD
McBSP0 receive frame sync
FSX0
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used, unless otherwise noted.)
§To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
E3
I/O/Z
IPD
McBSP0 transmit frame sync
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