參數(shù)資料
型號： TMP320R2811PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 67/147頁
文件大?。?/td> 2021K
代理商： TMP320R2811PBKS
Peripherals
67
June 2004
SPRS257
4.5
Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
Compatible to McBSP in TMS320C54x
/TMS320C55x
DSP devices, except the DMA features
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
HIghly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
Works with SPI-compatible devices
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
McBSP clock rate = CLKG =
CCLKGDIV) , where CLKSRG source could be LSPCLK, CLKX, or CLKR.
(1
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum.
Figure 4
9 shows the block diagram of the McBSP module with FIFO, interfaced to the R281x version of
Peripheral Frame 2.
A
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
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