參數(shù)資料
型號： TMP320R2811PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 109/147頁
文件大?。?/td> 2021K
代理商： TMP320R2811PBKS
Electrical Specifications
109
June 2004
SPRS257
6.20
SPI Slave Mode Timing
Table 6
22. SPI Slave Mode External Timing (Clock Phase = 0)
NO.
12
MIN
MAX
UNIT
ns
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
4t
c(LCO)
0.5t
c(SPC)S
10
0.5t
c(SPC)S
10
0.5t
c(SPC)S
10
0.5t
c(SPC)S
10
13
§
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
ns
14
§
ns
15
§
t
d(SPCH-SOMI)S
0.375t
c(SPC)S
10
ns
t
d(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.375t
c(SPC)S
10
16
§
t
v(SPCL-SOMI)S
0.75t
c(SPC)S
ns
t
v(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75t
c(SPC)S
19
§
t
su(SIMO-SPCL)S
t
su(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0
0
ns
20
§
t
v(SPCL-SIMO)S
0.5t
c(SPC)S
ns
t
v(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5t
c(SPC)S
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
c(SPC)
= SPI clock cycle time = LS4
(SPIBRR
t
c(LCO)
= LSPCLK cycle time
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
or
LSPCLK
1)
A
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