參數(shù)資料
型號： TMP320F2812PBKQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 99/147頁
文件大?。?/td> 2021K
代理商： TMP320F2812PBKQ
Electrical Specifications
99
June 2004
SPRS257
XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
t
d(IDLE
XCOH)
32 SYSCLKOUT Cycles
X1/XCLKIN
XCLKOUT
HALT
HALT
Wake
up Latency
Flushing Pipeline
t
d(INT)
A
B
C
D
Device
Status
E
G
F
PLL Lock
up Time
XNMI
Normal
Execution
t
w(WAKE
XNMI)
t
p
Oscillator Start-up Time
Figure 6
12. HALT Wakeup Using XNMI
A
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