參數(shù)資料
型號(hào)： TMP320F2812PBKQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號(hào)處理器
文件頁數(shù)： 125/147頁
文件大?。?/td> 2021K
代理商： TMP320F2812PBKQ
Electrical Specifications
125
June 2004
SPRS257
6.28
XHOLD/XHOLDA Timing
Table 6
36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
MAX
UNIT
t
d(HL-HiZ)
t
d(HL-HAL)
t
d(HH-HAH)
t
d(HH-BV)
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
4t
c(XTIM)
5t
c(XTIM)
3t
c(XTIM)
4t
c(XTIM)
ns
ns
ns
ns
á
á
áá
áá
XCLKOUT
(/1 Mode)
XHOLD
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XD[15:0]
Valid
XHOLDA
t
d(HL-Hiz)
t
d(HH-HAH)
High-Impedance
XA[18:0]
Valid
Valid
High-Impedance
t
d(HH-BV)
t
d(HL-HAL)
See Note A
See Note B
NOTES: A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6
32. External Interface Hold Waveform
A
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