參數(shù)資料
型號： TMP320F2812PBKQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 130/147頁
文件大小： 2021K
代理商： TMP320F2812PBKQ
Electrical Specifications
130
June 2004
SPRS257
ac
R
s
ADCIN0
C
p
10 pF
R
on
1 k
1.25 pF
C
h
Switch
Typical Values of the Input Circuit Components:
Switch Resistance (R
on
):
Sampling Capacitor (C
):
Parasitic Capacitance (C
p
): 10 pF
Source Resistance (R
s
):
1 k
1.25 pF
50
28x DSP
Source
Signal
Figure 6
34. ADC Analog Input Impedance Model
6.29.4
ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
PWDNADC
Request for
ADC
Conversion
t
d(BGR)
t
d(PWD)
Figure 6
35. ADC Power-Up Control Bit Timing
Table 6
40. ADC Power-Up Delays
MIN
TYP
MAX
UNIT
t
d(BGR)
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the PWDNADC bit is enabled.
7
8
10
ms
t
d(PWD)
Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register
Delay time for power down control to be stable. Bit 7 of the ADCTRL3 register
(PWDNADC) is to be set to 1 before any ADC conversions are initiated.
20
50
μ
s
ms
1
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions
are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.
A
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