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參數(shù)資料
| 型號： | TMC2490A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Encoder |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻編碼器 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大小： | 510K |
| 代理商： | TMC2490A |
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TMC2490A
PRODUCT SPECIFICATION
12
REV. 1.0.2 2/27/02
Horizontal and Vertical Timing
Horizontal and vertical video timing in the TMC2490A is
preprogrammed for line-locked systems with a 2x pixel
clock of 27.0 MHz.
Table 3 and Table 4 show timing parameters for NTSC and
PAL standards and the resulting TMC2490A analog output
timing. The user provides exactly 720 pixels of active video
per line. In master mode, the TMC2490A precisely controls
the duration and activity of every segment of the horizontal
line and vertical field group. In external sync slave mode, it
holds the end-of-line blank state (e.g. front porch for active
video lines) until it receives the next horizontal sync signal.
In CCIR-656 slave mode, it likewise holds each end-of-line
blank state until it receives the next end of active video
(EAV) signal embedded in the incoming data stream.
The vertical field group comprises several different line
types based upon the Horizontal line time.
H
= (2 x SL) + (2 x SH) [Vertical sync pulses]
= (2 x EL) + (2 x EH) [Equalization pulses]
SMPTE 170M NTSC and Report 624 PAL video standards
call for specific rise and fall times on critical portions of the
video waveform. The chip does this automatically, requiring
no user intervention. The TMC2490A digitally defines
Figure 2a. HDEL TIming
Figure 2b. CCIR-656 Horizontal Interval Timing Detail
Figure 3. Master Mode Horizontal Interval Timing Detail
PXCK
PD
7-0
C
B732
Y
732
C
R732
Y
733
CBSEL
HYSNC
1464
1592
65-2490A-03
625-line
C
B734
Y
734
C
R734
Y
735
C
B736
Y
736
HDEL = 00
HDEL = 01
HDEL = 10
HDEL = 11
C
R736
C
B800
Y
800
C
R800
Y
801
C
B801
C
R856
Y
857
C
B0
Y
0
C
R0
Y
1
C
B2
0
0
1727
PXCK
PD
7-0
1430
FF
FF
00
00
FV
1
HSYNC (Output)
HDEL = 2
PDC
00
00
FV
0
C
B0
Y
0
1440
1464
1724
t
DO
t
HP
t
SP
1727
17
3
0
0
65-2490A-04
625-line
t
DO
t
DO
t
HS
SAV
EAV
PXCK
PD
7-0
1430
HSYNC (Output)
HDEL = 2
PDC
C
B0
Y
0
1440
1464
17
3
t
DO
t
H
t
S
1727
0
0
65-2490A-05
625-line
t
DO
t
DO
t
HS
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