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參數(shù)資料
| 型號： | TMC2302AH5C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PPGA120 |
| 封裝： | CAVITY-UP, PLASTIC, PGA-120 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大小： | 188K |
| 代理商： | TMC2302AH5C |
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PRODUCT SPECIFICATION
TMC2302A
25
P
A more efficient method is to divide the original source
image into a “four-color checker board” and to store it into
four separate pixel memory banks, each containing 14th
of the source image. Since the image is separated into
four memories rather than duplicated, no additional image
memory is required. The goal is to separate the image so that
any square of four adjacent pixel locations can be accesssed
simultaneously. Thus, the user must organize the memory
such that the four pixels of any cluster will reside in separate
memory banks. With this method, only one set of address
generators (TMC2302As) is necessary, and only a slight
address modification is necessary to guarantee that the
correct group of pixels is accessed and output to the multipli-
ers. Since all pixels are accessed simultaneously, no “walk”
is performed, and the TMC2302A system is able to generate
one destination pixel on each clock cycle. For example, a
1024 x 768 image can be generated every 20ms for a frame
refresh rate of 50Hz. This method which will be described
below.
Using Banded Pixel Memory
The TMC2302A should be programmed to do “nearest-
neighbor” transformations (Kernel, K = 0 and the X
0
and Y
0
start boundaries programmed without 1/2-LSB truncation
debiasing to force address truncation when evaluating the
transformation polynomial for the nearest-pixel address).
The biased X
0
and Y
0
guarantee that when the exact pixel
address falls within the region of four pixels, the upper left-
most pixel will always be selected as “nearest-neighbor.”
The key to performing real-time bilinear interpolation is to
arrange the pixels in memory so that the four pixels of every
grouping will be stored in separate memories. The four near-
est pixels will form a square. Figure 11 shows a sample
512 x 512 pixel image and the arrangement into four sepa-
rate memory banks designated A, B, C, and D. It can be seen
from the figure that any (square) grouping of four pixels will
have one pixel located in each bank. Thus, one memory
sector will hold even row-even column pixels, another,
even-row-add column pixels, etc.
Figure 11. Source Image Pixel Arrangement
A
0,0
(0,0)
B
0,0
(1,0)
A
1,0
(2,0)
B
1,0
(3,0)
A
2,0
(4,0)
B
2,0
(5,0)
A
3,0
…A
255,0
(6,0)…(510, 0)
B
255.0
(511, 0)
C
0,0
(0,1)
D
0,0
(1,1)
C
1,0
(2,1)
D
1,0
(3,1)
C
2,0
(4,1)
D
2,0
(5,1)
C
3,0
…C
255,0
(6,1)…(510,1)
D
255,0
(511,1)
A
0,1
(0,2)
B
0,1
(1,1)
A
1,1
(2,1)
B
1,1
(3,2)
A
2,1
(4,2)
B
2,1
(5,2)
A
3,1
…A
255,1
(6,2)…(510,2)
B
255,1
(511,2)
C
0,1
(0,3)
D
0,1
(1,3)
C
1,1
(2,3)
D
1,1
(3,3)
C
2,1
(4,3)
D
2,1
(5,3)
C
3,1
…C
255,1
(6,3)…(510,3)
D
255,1
(511,3)
A
0,2
(0,4)
B
0,2
(1,4)
A
1,2
(2,4)
B
l,2
(3,4)
A
2,2
(4,4)
B
2,2
(5,4)
A
3,2
…A
255,2
(6,4)…(510,4)
B
255,2
(511,4)
C
0,2
(0,5)
D
0,2
(1,5)
C
1,2
(2,5)
D
1,2
(3,5)
C
2,2
(4,5)
D
2,2
(5,5)
C
3,2
…C
255,2
(6,5)…(510,5)
D
255,2
(511,5)
…
…
…
…
…
…
…
…
A
0,255
(0,510)
B
0,255
(1,510)
A
1,255
(2,510)
B
1,255
(3,510)
A
2,255
(4,510)
B
2,255
(5,510)
A
3,255
…A
255,255
(6,510)…(510,510)
B
255,255
(511,510)
C
0,255
(0,511)
D
0,255
(1,511)
C
1,255
(2,511)
D
1,255
(3,511)
C
2,255
(4,511)
D
2,255
(5,511)
C
3,255
…C
255,255
(6,511)…(510,511)
D
255,255
(511,511)
Subscripts i, j for A, B, C, and D denote relative addresses in
memory respectively.
The ordered pairs (a, b) denote the physical (X,Y) pixel
locations and the TMC2302A SAPR(X) and SADR(Y)
address outputs.
The pixels of the original image should be stored in the
source RAM banks as shown in Figure 12. The original
source image can be loaded by decoding the TMC2302A
least significant address bits (SADR
X
(8). SADR
Y
(8) to
determine the memory bank for the pixel while the
most-significant address bits (SADR
X
(19:9), SADR
Y
(19:9))
are used as common address lines to all four memory banks.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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