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參數(shù)資料
| 型號： | TMC2193KJC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | 10 Bit Encoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 448K |
| 代理商： | TMC2193KJC |
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TMC2193
PRODUCT SPECIFICATION
32
REV. 1.0 3/26/03
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state t
DOZ
after CS falls. Valid data are
present on D7-0 t
DOM
after the falling edge of CS. Because
this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
PXCK period. This uncertainty does not apply to t
DOZ
.
Writing data to specific control registers of the TMC2193
requires that the 8 bit address of the control register of inter-
est be written prior to the data. This control register address
is the base address for subsequent write operations. The base
address auto increments by one for each byte of data written
after the data byte intended for the base address. If more
bytes are transferred than there are available addresses, the
address will not increment and remain at its maximum value
of 4Ch.
Writing data to specific OLUT location of the TMC2193
requires that the 8 bit address of the OLUT location of inter-
est be written prior to the data sequence. This OLUT loca-
tion address is the base address for subsequent write
operations. The base address auto increments by one for
each sequence of three (3) bytes of data written after the data
byte intended for the base address. The sequence of data
transfer is Y or Green, C
b
or Blue, C
r
or Red, after the C
r
or
Red byte is transferred the base address will increment by
one (1).
Figure 24. Microprocessor Parallel Port
–
Write Timing
Figure 25. Microprocessor Parallel Port
–
Read Timing
Table 24. Parallel Port Control
A
1-0
00
R/W
0
Action
Load D
7-0
into Control Register
pointer (block 0)
Read Control Register pointer on
D
7-0
Load D
7-0
into addressed OLUT
Location pointer (block 0)
Read addressed OLUT Location
pointer on D
7-0
.
Write D
7-0
to addressed Control
Register
Read addressed Control Register
on D
7-0
Write D
7-0
to addressed OLUT
Location
Read addressed OLUT Location on
D
7-0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
t
PWLCS
t
SA
t
SD
t
HA
t
HD
t
PWHCS
CS
65-6294-26
R/W
ADR
D
7-0
t
PWLCS
t
SA
t
DOM
t
HA
t
HOM
t
DOZ
t
PWHCS
CS
R/W
ADR
D
7-0
65-6294-27
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