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| 型號： | TM248GBK32-80 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DYNAMIC RAM MODULES |
| 中文描述： | 動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 158K |
| 代理商： | TM248GBK32-80 |
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAMMODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended range of supply voltage and operating free-air
temperature
’124FBK32-60
’248GBK32-60
’124FBK32-70
’248GBK32-70
’124FBK32-80
’248GBK32-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
tRWC
tRASP
tRAS
tRP
tWP
tRASS
tRPS
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWRP
tCAH
tDH
tRAH
tRCH
tRRH
tWCH
tWRH
tRHCP
tCHS
tCHR
tCRP
tCSR
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tREF
tT
NOTES:
Cycle time, random read or write (see Note 7)
110
130
150
ns
Cycle time, read-write
150
175
200
ns
Pulse duration, page-mode, RAS low
60
100 000
70
100 000
80
100 000
ns
Pulse duration, non-page-mode, RAS low
60
10 000
70
10 000
80
10 000
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
μ
s
ns
Pulse duration, self-refresh entry from RAS low
100
100
100
Pulse duration, RAS precharge after self-refresh
110
130
150
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before CAS low
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
Setup time, W low before CAS high
10
12
15
ns
Setup time, W low before RAS high
10
12
15
ns
Setup time, W low before CAS low
0
0
0
ns
Setup time, W high before RAS low (see Note 8)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
Hold time, data after CAS low
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, W high after CAS high (see Note 9)
0
0
0
ns
Hold time, W high after RAS high (see Note 9)
0
0
0
ns
Hold time, W low after CAS low
10
15
15
ns
Hold time, W high after RAS low (see Note 8)
10
10
10
ns
Hold time, RAS high from CAS precharge
35
40
45
ns
Hold time, CAS low after RAS high (self-refresh)
– 50
– 50
– 50
ns
Delay time, RAS low to CAS high (see Note 8)
10
10
10
ns
Delay time, CAS high to RAS low
5
5
5
ns
Delay time, CAS low to RAS low (see Note 8)
5
5
5
ns
Delay time, RAS low to column address (see Note 10)
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
20
25
30
ns
Delay time, RAS low to CAS low (see Note 10)
20
45
20
52
20
60
ns
Delay time, RAS high to CAS low (CBR only)
0
0
0
ns
Delay time, CAS low to RAS high
10
12
15
ns
Refresh time interval
16
16
16
ms
Transition time
2
30
2
30
2
30
ns
7. All cycled times assume tT = 5 ns.
8. CBR refresh only
9. Either tRRH or tRCH must be satisfied for a read cycle.
10. Maximum value specified only to assure access time.
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