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TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAMMODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
’248GBK32-60
MIN
2.4
’248GBK32-70
MIN
2.4
’248GBK32-80
MIN
2.4
UNIT
MAX
MAX
MAX
VOH
VOL
High-level output voltage
IOH = – 5 mA
IOL = 4.2 mA
VI = 0 to 6.5 V,
All other pins = 0 to VCC
VO = 0 to VCC,
CAS high
V
Low-level output voltage
0.4
0.4
0.4
V
II
Input current (leakage)
VCC = 5 V,
±
20
±
20
±
20
μ
A
IO
Output current (leakage)
VCC = 5.5 V,
±
20
±
20
±
20
μ
A
ICC1
Read- or write-cycle current
(see Note 3)
Minimum cycle,
VCC = 5.5 V
856
736
656
mA
ICC1
Standby current
After one memory cycle,
RAS and CAS high,
VIH=2.4 V (TTL)
After one memory cycle,
RAS and CAS high,
VIH = VCC – 0.2 V (CMOS)
Minimum cycle,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
32
32
32
mA
16
16
16
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
VCC = 5.5 V,
1680
1440
1280
mA
ICC4
Average EDO current
(see Note 4)
tPC = minimum,
RAS low, CAS cycling
VCC = 5.5 V,
736
656
576
mA
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature
f = 1 MHz (see Note 5)
’124FBK32
MIN
’248GBK32
MIN
UNIT
MAX
MAX
Ci(A)
Ci(R)
Ci(C)
Ci(W)
Co(DQ)
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pins under test is 0 V.
Input capacitance, address inputs
40
80
pF
Input capacitance, RAS
28
28
pF
Input capacitance, CAS
14
28
pF
Input capacitance, write-enable input
56
112
pF
Output capacitance on DQ pins
7
14
pF