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參數(shù)資料
| 型號： | TM16EN72LPU-40 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 EDO DRAM MODULE, 20 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 344K |
| 代理商： | TM16EN72LPU-40 |
TM16EN64HPU, TM16EN64LPU 16777216 BY 64BIT
TM16EN72HPU, TM16EN72LPU 16777216 BY 72BIT
EXTENDEDDATAOUT DYNAMIC RAM MODULES
SMMS695A AUGUST 1997 REVISED NOVEMBER 1997
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM16EN72LPU
PARAMETER
TEST CONDITIONS
’16EN72LPU-40
’16EN72LPU-50
’16EN72LPU-60
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
High-level
output
IOH = 2 mA
LVTTL
2.4
V
VOH
output
voltage
IOH = 100 A
LVCMOS
VDD 0.2
V
VOL
Low-level
output
IOL = 2 mA
LVTTL
0.4
V
VOL
output
voltage
IOL = 100 A
LVCMOS
0.2
V
II
Input
current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 20
A
IO
Output
current
(leakage)
VDD = 3.6 V,
VO = 0 V to VDD,
CASx high
± 20
A
ICC1§
Average
read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
2250
1800
1620
mA
Average
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
18
mA
ICC2
Average
standby
current
VIH = VDD 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
9
mA
ICC3§
Average
refresh
current
(RAS-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
2250
1800
1620
mA
ICC4
Average
EDO
current
VDD = 3.6 V,
tHPC = MIN,
RASx low,
CASx cycling
2520
1980
1620
mA
ICC5§
Average
CBR
refresh
current
VDD = 3.6 V,
Minimum cycle,
RASx low after CASx low
2880
2340
1980
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
Measured with a maximum of one address change during each EDO cycle, tHPC
PRODUCT
PREVIEW
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