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參數(shù)資料
| 型號： | TLV986CPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 266K |
| 代理商： | TLV986CPFB |
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JULY 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
internal timing
Operating the CDS requires signals SR and SV as previously explained. The user needs to synchronize the
SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external circuitry by the
ADCCLK signal that is also used internally to control both ADC and PGA operations. It is necessary that the
positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses as shown in Figure 1.
The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal performance.
The TLV986 has direct access to the CDS and PGA internal clocks through the TPP and TPM terminal. The
TPP and TPM assist the user in timing alignment. See
Test Register Description for details.
The CLAMP signal activates the input clamping and the OBCLP signal activates auto optical black and offset
correction.
input blanking function
During some period of operation, large input transients may occur at the TLV986’s input, saturating the input
circuits and causing long recovery time. To prevent the circuit saturation, the TLV986 includes an input blanking
function that blocks the input signals by disabling the CDS operation whenever the BLKG input is pulled low.
3-wire serial interface
A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of
the TLV986. The serial clock SCLK can be run at a maximum speed of 40 MHz. The serial data SDIN is 16 bits
long. After two leading null bits, there are four address bits for which internal register is to be updated; the
following ten bits are the data to be written to the register. To enable the serial port, the CS pin must be held
low. The data transfer is initiated by the incoming SCLK after the CS falls.
device reset
When the reset (terminal 29) is pulled low, all internal registers are set to their default values. The device also
resets itself when it is first powered on. In addition, the TLV986 has a software-reset function that resets the
device when writing a control bit to the control register. See
Register Definition section for the register default
values.
device reset
When the reset (terminal 29) is pulled low, all internal registers are set to their default values. The device also
resets itself when it is first powered on. In addition, the TLV986 has a software-reset function that resets the
device when writing a control bit to the control register. See
Register Definition section for the register default
values.
power-down mode (standby)
The TLV986 has both hardware and software power–down modes. Pulling the STBY (terminal 30) low puts the
device in the low-power standby mode. Total supply current drops to ~0.6 mA. Setting a power-down control
bit in the control register can also activate the power-down mode. The user can still program all internal registers
during the power-down mode.
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| TLV986PFB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR |
| TLV987 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR |
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