參數(shù)資料
型號: TLV5625D
廠商: Texas Instruments, Inc.
英文描述: 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
中文描述: 2.7 V至5.5 V的低功耗雙8位數(shù)字至模擬轉(zhuǎn)換器與電源向下
文件頁數(shù): 5/15頁
文件大?。?/td> 194K
代理商: TLV5625D
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
Ci
High-level digital input current
VI = VDD
VI = 0 V
1
Low-level digital input current
–1
Input capacitance
8
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
2.5
MAX
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
See Note 11
CL = 100 pF,
Fast
μ
s
,
Slow
12
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code to code
RL = 10 k
See Note 12
CL = 100 pF,
Fast
1
μ
s
,
Slow
2
SR
Slew rate
RL = 10 k
See Note 13
CL = 100 pF,
Fast
3
V/
μ
s
,
Slow
0.5
Glitch energy
DIN = 0 to 1,
CS = VDD
FCLK = 100 kHz,
5
nV–s
SNR
Signal-to-noise ratio
52
54
SINAD
Signal-to-noise + distortion
fs = 102 kSPS, fout
RL = 10 k
,
48
49
dB
THD
Total harmonic distortion
CL = 100 pF
,
–50
–48
SFDR
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
Spurious free dynamic range
48
50
P
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