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參數(shù)資料
| 型號： | TLV5625D |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| 中文描述： | 2.7 V至5.5 V的低功耗雙8位數(shù)字至模擬轉(zhuǎn)換器與電源向下 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 194K |
| 代理商： | TLV5625D |
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial
interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by the reference) is given by:
2 REF0x1000[V]
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0. A power-on
reset initially puts the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 2 shows examples of how to connect the TLV5625 to TMS320, SPI
, and Microwire
.
TMS320
DSPFSX
CLKX
DX
TLV5625
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5625
CS
SCLK
DIN
Microwire
I/O
SO
SK
TLV5625
SCLK
DIN
CS
Figure 12. Three-Wire Interface
Notes on SPI
and Microwire
: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS. If the word width is 8 bits (SPI
and Microwire
) two write operations
must be performed to program the TLV5625. After the write operation(s), the holding registers or the control
register are updated automatically on the 16
th
positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax
1
t
whmin
t
wlmin
20 MHz
The maximum update rate is:
f
updatemax
1
16 t
whmin
t
wlmin
1.25 MHz
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5625 should also be considered.
P
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