參數(shù)資料
型號(hào): TLV320DAC3100IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: DAC WITH PROGRAMMABLE PLL, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù): 51/97頁(yè)
文件大?。?/td> 1134K
代理商: TLV320DAC3100IRHBR
LD (n)
LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
3
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD (n)
LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N
-
3
RD (n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
4
3
2
5
1
0
-
1
4
3
2
5
1
0
N
-
1
5
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
www.ti.com
SLAS671 – FEBRUARY 2010
Figure 5-26. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock
For the left-justified mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
5.7.1.3
I2S Mode
The audio interface of the TLV320DAC3100 can be put into I2S mode by programming page 0 /
register 27, bits D7–D6 = 00. In I2S mode, the MSB of the left channel is valid on the second rising edge
of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on
the second rising edge of the bit clock after the rising edge of the word clock.
Figure 5-27. Timing Diagram for I2S Mode
Figure 5-28. Timing Diagram for I2S Mode With Offset = 2
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
55
Product Folder Link(s): TLV320DAC3100
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