參數(shù)資料
型號(hào): TLV320AIC31IRHBTG4
廠商: Texas Instruments
文件頁(yè)數(shù): 14/84頁(yè)
文件大小: 0K
描述: IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝: 250
類型: 立體聲音頻
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 100
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 100
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 帶卷 (TR)
配用: 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
RIGHT-JUSTIFIED MODE
BCLK
WCLK
SDIN/
SDOUT
1
0
1
0
1/fs
LSB
MSB
LeftChannel
RightChannel
2
n1
n3
n2
n1
n3
n2
LEFT-JUSTIFIED MODE
n-1 n-2
n-3
n-1 n-2
n-3
I
2S MODE
n-1
n-2 n-3
n-1
n-2 n-3
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 18. Right-Justified Serial Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Figure 19. Left-Justified Serial Data Bus Mode Operation
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
Figure 20. I2S Serial Data Bus Mode Operation
Copyright 2006–2008, Texas Instruments Incorporated
21
Product Folder Link(s): TLV320AIC31
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