參數(shù)資料
型號： TLV320AIC31IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 35/83頁
文件大?。?/td> 1197K
代理商： TLV320AIC31IRHBT
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
Page 0 / Register 4:
PLL Programming Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
000001
PLL J Value
000000: Reserved, do not write this sequence
000001: J = 1
000010: J = 2
000011: J = 3
…
111110: J = 62
111111: J = 63
D1–D0
R/W
00
Reserved; write only '0' to these bits
Page 0 / Register 5:
PLL Programming Register C(1)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00000000
PLL D value. Eight most significant bits of a 14-bit unsigned integer valid values for D are from 0
to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written
into these registers that would result in a D value outside the valid range.
(1)
Note that whenever the D value is changed, Register 5 should be written, immediately followed by Register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Page 0 / Register 6:
PLL Programming Register D
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
000000
PLL D value. Six least significant bits of a 14-bit unsigned integer valid values for D are from 0 to
9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written
into these registers that would result in a D value outside the valid range.
D1-D0
R
00
Reserved; write only '0' to these bits.
Page 0 / Register 7:
Codec Datapath Setup Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
FSref setting
This register setting controls timers related to the AGC time constants.
0: FSref = 48 kHz
1: FSref = 44.1 kHz
D6
R/W
0
ADC Dual rate control
0: ADC dual rate mode is disabled
1: ADC dual rate mode is enabled
Note: ADC Dual Rate Mode must match DAC Dual Rate Mode
D5
R/W
0
DAC Dual Rate Control
0: DAC dual rate mode is disabled
1: DAC dual rate mode is enabled
D4–D3
R/W
00
Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D2–D1
R/W
00
Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
D0
R/W
0
Reserved. Only write '0' to this register.
40
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV320AIC31IRHBT 制造商:Texas Instruments 功能描述:IC CODEC STEREO AUDIO 32-VQFN
TLV320AIC31IRHBTG4 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC32 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
TLV320AIC32_07 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
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