SHORT-CIRCUIT OUTPUT PROTECTION
CONTROL REGISTERS
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
When these output drivers are powered down, they can be placed into a variety of output conditions based on
register programming. If lowest power operation is desired, then the outputs can be placed into a 3-state
condition, and all power to the output stage is removed. However, this generally results in the output nodes
drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results
in a longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this required
power-on delay, the TLV320AIC31 includes an option for the output pins of the drivers to be weakly driven to the
VCM level they would normally rest at when powered with no signal applied. This output VCM level is determined
by an internal bandgap voltage reference, and thus results in extra power dissipation when the drivers are in
power-down. However, this option provides the fastest method for transitioning the drivers from power-down to
full power operation without any output artifact introduced.
The device includes a further option that falls between the other two: while it requires less power drawn while the
output drivers are in power-down, it also takes a slightly longer delay to power-up without artifacts than if the
bandgap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a
voltage of approximately half the DRVDD supply level using an internal voltage divider. This voltage will not
match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a
much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output
The high-power output drivers can also be programmed to power up first with the output level control in a
highly-attenuated state, then the output driver will automatically slowly reduce the output attenuation to reach the
desired output level setting programmed. This capability is enabled by default but can be enabled in
The TLV320AIC31 includes programmable short-circuit protection for the high-power output drivers, for maximum
flexibility in a given application. By default, if these output drivers are shorted, they will automatically limit the
maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an
over-current condition. In this mode, the user can read
Page-0/Reg-95 to determine whether the part is in
short-circuit protection or not, and then decide whether to program the device to power down the output drivers.
However, the device includes further capability to automatically power down an output driver whenever it does
into short-circuit protection, without requiring intervention from the user. In this case, the output driver will stay in
a power down condition until the user specifically programs it to power down and then power back up again, to
clear the short-circuit flag.
The control registers for the TLV320AIC31 are described in detail below. All registers are 8-bit in width, with D7
referring to the most significant bit of each register, and D0 referring to the least significant bit.
Page 0 / Register 0:
Page Select Register
BIT(1)
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D1
X
0000000
Reserved; write only 0s to these register bits
D0
R/W
0
Page Select Bit
Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a
one to this bit sets Page-1 as the active page for following register accesses. It is recommended
that the user read this register bit back after each write, to ensure that the proper page is being
accessed for future register read/writes.
(1)
When resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to
the registers instead of using software reset.
Page 0 / Register 1:
Software Reset Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
W
0
Software Reset Bit
0 : Don’t Care
1 : Self clearing software reset
D6–D0
W
0000000
Reserved; don’t write
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