參數(shù)資料
型號(hào)： TLV320AIC3110IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 95/126頁(yè)
文件大小： 1528K
代理商： TLV320AIC3110IRHBT
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PLL _ CLKIN
10 MHz
20 MHz
P
SLAS647 – DECEMBER 2009
www.ti.com
When the PLL is enabled and D
≠ 0, the following conditions must be satisfied for PLL_CLKIN:
(11)
80 MHz
≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz
R = 1
The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a
general-purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is
available typically after 10 ms.
The clocks for codec and various signal processing blocks, CODEC_CLKIN can be generated from MCLK
input, BCLK input, GPIO input or PLL_CLK (page 0 / register 4, bits D1–D0).
If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down
last.
Table 5-42 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to
achieve a sample rate fS of either 44.1 kHz or 48 kHz.
Table 5-42. PLL Example Configurations
fS = 44.1 kHz
PLL_CLKIN
PLLP
PLLR
PLLJ
PLLD
MADC
NADC
AOSR
MDAC
NDAC
DOSR
(MHz)
2.8224
1
3
10
0
3
5
128
3
5
128
5.6448
1
3
5
0
3
5
128
3
5
128
12
1
7
560
3
5
128
3
5
128
13
1
6
3504
2
9
104
6
3
104
16
1
5
2920
3
5
128
3
5
128
19.2
1
4
4100
3
5
128
3
5
128
48
4
1
7
560
3
5
128
3
5
128
fS = 48 kHz
2.048
1
3
14
0
2
7
128
7
2
128
3.072
1
4
7
0
2
7
128
7
2
128
4.096
1
3
7
0
2
7
128
7
2
128
6.144
1
2
7
0
2
7
128
7
2
128
8.192
1
4
3
0
2
8
128
4
128
12
1
7
1680
2
7
128
7
2
128
16
1
5
3760
2
7
128
7
2
128
19.2
1
4
4800
2
7
128
7
2
128
48
4
1
7
1680
2
7
128
7
2
128
5.7
Digital Audio and Control Interface
5.7.1
Digital Audio Interface
Audio data is transferred between the host processor and the TLV320AIC3110 via the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified
data options, support for I2S or DSP protocols, programmable data-length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TLV320AIC3110 can be configured for left- or right-justified, I2S, DSP, or TDM
modes of operation, where communication with standard telephony interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
70
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3110
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