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| 型號(hào)： | TLV320AIC3110IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁(yè)數(shù)： | 91/126頁(yè) |
| 文件大?。?/td> | 1528K |
| 代理商： | TLV320AIC3110IRHBT |
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www.ti.com
SLAS647 – DECEMBER 2009
Table 5-40. CODEC CLKIN Clock Dividers
Divider
Bits
NDAC
Page 0 / register 11, bits D6–D0
MDAC
Page 0 / register 12, bits D6–D0
DOSR
Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0
NADC
Page 0 / register 18, bits D6–D0
MADC
Page 0 / register 19, bits D6–D0
AOSR
Page 0 / register 20, bits D7–D0
The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,
these clocks must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11,
bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device
internally initiates a power-down sequence for proper shutdown. During this shutdown sequence, the
NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not take
place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 /
register 37, bit D3. When both the flags indicate power down, the MDAC divider may be powered down,
followed by the NDAC divider. Note that when the ADC clock dividers are powered down, the ADC clock
is derived from the DAC clocks.
The ADC modulator is clocked by ADC_MOD_CLK. For proper power-up of the ADC channel, these
clocks are enabled by the NADC and MADC clock dividers (page 0 / register 18, bit D7 = 1 and page 0 /
register 19, bit D7 = 1). When the ADC channel is powered down, the device internally initiates a
power-down sequence for proper shutdown. During this shutdown sequence, the NADC and MADC
dividers must not be powered down, or else a proper low-power shutdown may not take place. The user
can read back the power-status flag from page 0 / register 36, bit D6. When this flag indicates
power-down, the MADC divider may be powered down, followed by NADC divider.
When ADC_CLK (ADC processing clock) is derived from the NDAC divider output, the NDAC must be
kept powered up until the power-down status flags for ADC do not indicate power down. When the input to
the AOSR clock divider is derived from DAC_MOD_CLK, then MDAC must be powered up when ADC_fS
is needed (i.e., when WCLK is generated by TLV320AIC3110 or AGC is enabled) and can be powered
down only after the ADC power-down flags indicate power-down status.
In general, all the root clock dividers should be powered down only after the child clock dividers have been
powered down for proper operation.
The TLV320AIC3110 also has options for routing some of the internal clocks to the output pins of the
device to be used as general-purpose clocks in the system. The feature is shown in Figure 5-37.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
67
Product Folder Link(s): TLV320AIC3110
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