參數(shù)資料
型號(hào)： TLV2211Y
廠(chǎng)商： Texas Instruments, Inc.
英文描述： Advanced LinCMOSE RAIL-TO-RAIL MICROPOWER SINGLE OPERATIONAL AMPLIFIERS
中文描述： 高級(jí)LinCMOSE軌至軌微功耗單運(yùn)算放大器
文件頁(yè)數(shù)： 27/29頁(yè)
文件大?。?/td> 529K
代理商： TLV2211Y
TLV2211, TLV2211Y
Advanced LinCMOS
RAIL-TO-RAIL
MICROPOWER SINGLE OPERATIONAL AMPLIFIERS
SLOS156B – MAY 1996 – REVISED JANUARY 1997
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 6) and subcircuit in Figure 53 are generated using
the TLV2211 typical electrical and operating characteristics at T
A
= 25
°
C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits,SC-9, 353 (1974).
OUT
+
–
+
–
53
+
–
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TLV2211 1 2 3 4 5
C1
C2
DC
DE
DLP
DLN
DP
EGND
FB
+ VLN 0 4.29E6 –6E6 6E6 6E6 –6E6
GA
6
GCM
0
ISS
3
HLIM
90
J1
11
J2
12
R2
6
11
6
5
54
90
92
4
99
7
12
7
53
5
91
90
3
0
99
8.86E–12
50.00E–12
DX
DX
DX
DX
DX
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
0
6
10
0
2
1
9
11
10
DC 1.250E–6
VLIM 1K
10 JX
10 JX
100.0E3
12 9.425E–6
99 1320.2E–12
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
VLIM
VLP
VLN
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=500.0E–15 BETA=166E–6
+ VTO=–.004)
.ENDS
60
60
8
7
3
10
60
9
3
54
7
91
0
11
12
5
99
4
99
4
0
53
4
8
0
92
106.1E3
106.1E3
50
150
419.2E3
160.0E6
–.5
DC 0
DC .55
DC .55
DC 0
DC 0.1
DC 2.6
VDD+
RP
IN –
2
IN+
1
VDD–
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 53. Boyle Macromodel and Subcircuit
PSpice and Partsare trademark of MicroSim Corporation.
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