參數(shù)資料
型號: TLK2201I
廠商: Texas Instruments, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Aluminum Alloy; Series:ACA-B Reverse Bayonet; No. of Contacts:7; Connector Shell Size:16S; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Gender:Female
中文描述: 以太網(wǎng)收發(fā)器
文件頁數(shù): 12/19頁
文件大?。?/td> 263K
代理商: TLK2201I
TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C
JUNE 2000
REVISED NOVEMBER 2001
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
transmitter/receiver characteristics
PARAMETER
TEST CONDITIONS
Rt = 50
Rt = 75
Rt = 50
Rt = 75
MIN
600
800
1000
1000
TYP
850
1050
1250
1250
MAX
1100
1200
1400
1400
UNIT
Vod = |TxD TxN|
mV
V(cm)
Transmit common mode voltage range
mV
Receiver Input voltage requirement,
Vid = |RxP
RxN|
200
1600
mV
Receiver common mode voltage range,
(RxP + RxN)/2
1000
1250
2250
mV
Ilkg(R)
CI
Receiver input leakage current
Receiver input capacitance
350
350
μ
A
pF
2
t(TJ)
Serial data total jitter (peak-to-peak)
Differential output jitter, Random
+ deterministic, PRBS pattern,
R
ω
= 125 MHz
Differential output jitter, PRBS
pattern, R
ω
= 125 MHz
RL = 50
, CL = 5 pF,
See Figures 7 and 8
0.24
UI
t(DJ)
Serial data deterministic jitter (peak-to-peak)
0.12
UI
tr, tf
Differential signal rise, fall time (20% to 80%)
100
250
ps
Serial data jitter tolerance minimum required eye
opening, (per IEEE-802.3 specification)
Differential input jitter, Random
+ deterministic, R
ω
= 125 MHz
0.25
UI
Receiver data acquisition lock time from powerup
Data relock time from loss of synchronization
500
1024
20
30
31
34
μ
s
Bit times
td(T l t
td(Tx latency)
Tx latency
TBI modes
DDR mode
TBI modes
DDR mode
See Figure 1
19
29
21
27
UI
td(Rx latency)
Rx latency
See Figure 6
UI
80%
50%
20%
tr
tr
tf
tf
80%
50%
20%
V
V
V
V
80%
20%
0 V
1V
1V
TX+
TX
VOD
Figure 7. Differential and Common-Mode
Output Voltage Definitions
CL
5 pF
CL
5 pF
50
50
Figure 8. Transmitter Test Setup
tr
tf
CLOCK
80%
50%
20%
tr
tf
2 V
0.8 V
DATA
1.4 V
Figure 9. TTL Data I/O Valid Levels for AC Measurement
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