![](http://datasheet.mmic.net.cn/390000/TLC34076M-135_datasheet_16838079/TLC34076M-135_38.png)
2–22
2.12.1
The TLC34076M provides a means to check all the data entering the DAC (but before the output multiplexer
8/6 shift). When accessing these color channels, the data entering the DACs should be kept constant for
the entire MPU read cycle. This can be done either by slowing down the dot clock or ensuring that the data
is constant for a sufficiently long series of pixels. The value read is the data stored in the color palette location
addressed by the data in the input multiplexer. The read operation causes a postincrement to point to the
next color channel, and the postincrement of blue wraps back to red as shown in the preceding state
diagram. For example, if D<2:0> is written as 001, then three successive reads are performed and the values
read out are green, blue, and red in that sequence.
Frame-Buffer Data Flow Test
2.12.2
The ID code can be used as a software identification for different versions. The ID code in the TLC34076M
is static and can be read without consideration of the dot clock or video signals. In order to be user-friendly,
the read postincrement applies to the ID register as well; however, when the state machine falls into the color
channel, it does not return to the ID code unless the user writes 011 (binary) to D2, D1, and D0 again.
Suppose the test register was first written as 011 (binary) in D2, D1, and D0. Then, when six successive
reads are performed, the first value read is the ID and the last value read is the green. The ID value defined
for the TLC34076M is 76 (HEX).
Identification Code
2.12.3
A technique called ones accumulation can be used to detect errors in fixed (not animated) screen displays.
This type of error detection is useful for system checkout and field diagnostics.
Ones-Accumulation Screen Integrity Test
Each of the 256 24-bit words in the TLC34076M internal color-palette RAM is composed of three bytes, one
each for the red, green, and blue components of the word. When D<2:0> are programmed with the
appropriate binary value (see Table 2–9), the TLC34076M monitors the corresponding color byte that is
output by the color-palette RAM. For example, if D<2:0> are programmed with the value 100, the
TLC34076M monitors the red byte. As the current frame is scanned, for each color-palette-RAM word
accessed, the designated color byte is checked to see how many 1 bits it contains and this number is added
to a temporary accumulator (the entire byte is checked, even if 6-bit mode is selected). For example, if the
designated color byte contains the value 41h (0100 0001), then the value 2 is added to the temporary
accumulator as 41h contains two 1 bits. This process is continued until an entire frame has been scanned;
the same color byte is monitored for the entire frame. The temporary accumulator truncates any overflow
above the value 255. Due to circuit speed limitations, the ones-accumulation is calculated at a speed of
(dot
-
clock frequency)/2. During the vertical retrace activated by a falling edge on the TLC34076M VSYNC
input, the value in the temporary accumulator is transferred into the ones-accumulation register, and then
the temporary accumulator is reset to zero (NOTE: the ones-accumulation register is updated only on the
falling edge of VSYNC, not by any vertical sync pulses coded into the composite video signal). Before the
next frame scan begins, the TLC34076M automatically changes the value in D<2:0> so that the ones
accumulation performed during the next frame scan is for a different color byte (see the screen integrity test
state diagram of Figure 2–11). As long as the screen display remains fixed, the ones-accumulation value
for a particular color byte should not change; if it does, an error has occurred.
Since ones accumulation is calculated at a dot clock/2 rate, there is uncertainty as to whether it start its
accumulation on an odd or even pixel. Regardless of whether the accumulation is performed on odd or even
pixels, subsequent screens are accumulated starting at the same point every time, unless the part is reset
or the internal dot
-
clock source changes.
2.12.4
An analog test is used to compare the voltage amplitudes of the analog RGB outputs to each other and to
a 145-mV reference. This enables the MPU to determine whether the CRT monitor is connected to the
analog RGB outputs or not and whether the DACs are functional. To perform an analog test, D<2:0> must
be set to 111; D<7:4> are set as shown in Table 2–11. D<3> contains the result of the analog test.
Analog Test