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參數(shù)資料
| 型號： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 30/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | TLC34076M-135 |
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2–14
2.4.6
The read-mask register is used to enable or disable a pixel address bit from addressing the color-palette
RAM. Each palette-address bit is logically ANDed with the corresponding bit from the read-mask register
before addressing the palette. This function is performed after the addition of the page-register bits, and a
zeroing of the read mask results in one unique palette location (location 0) and is not affected by the
palette-page-register contents.
The read mask can be used to zero the overlay data in the true-color modes. This is a handy way to disable
overlay (enable true-color data to the DACs) for a whole screen.
2.5
Reset
There are three ways to reset the TLC34076M:
1.
Power-on reset
2.
Hardware reset
3.
Software reset
2.5.1
Power-On Reset
There is a POR (power-on reset) circuit built into the TLC34076M. This POR works at power on only. Even
though this circuitry is provided, it is still recommended that the user design a hardware reset circuit to
ensure the reset condition after power up as described in section 2.5.2.
Once the voltage is stabilized, the default condition for all registers is the VGA mode. When the TLC34076M
is reset, the SCLK and VCLK counters are reset as well. See Sections 2.3 and 2.5.4.
2.5.2
Hardware Reset
The TLC34076M resets whenever RS<3:0> = HHHH and a rising edge occurs on the WR input. The more
rising WR edges occur, the more reliable the TLC34076M is reset. This scheme (bursting WR strobes until
the power supply voltage stabilizes) is suggested at power up if a hardware reset approach is used.
The default reset condition is the VGA mode, and the values for each register are shown in Section 2.5.4.
When the TLC34076M is reset, the SCLK and VCLK counters are reset. See Section 2.3.
2.5.3
Software Reset
Whenever the multiplex-control register is set for VGA pass-through mode after power up, all registers are
initialized accordingly. Since VGA pass-through mode is the default condition at power up and hardware
reset, the act of selecting the VGA pass-through mode through programming the multiplex-control register
is viewed as a software reset. Therefore, whenever multiplex-control-register bits <5:0> are set to 2Dh, the
TLC34076M initiates a software reset. This also resets the SCLK and VCLK counters (see 2.3). This is
referred to as a software reset since it is typically initiated by software, unlike POR or hardware resets.
2.5.4
VGA Pass-Through-Mode Default Conditions
The value contained in each register after hardware or software reset is shown below:
Multiplex-control register:
2Dh
Input-clock-selection register:
00h
Output-clock-selection register: 3Fh
Palette-page register:
00h
General-control register:
03h
Pixel read-mask register:
FFh
Palette-address register:
xxh
Palette-holding register:
xxh
Test register:
(pointing to color palette red value)
2.6
Frame-Buffer Interface
The TLC34076M provides two clock signals for controlling the frame-buffer interface: SCLK and VCLK.
SCLK can be used to clock out data directly from the VRAM shift registers. Split shift-register-transfer
Read Masking
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