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參數(shù)資料
| 型號： | TLC320AD90CFN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC64 |
| 封裝： | PLASTIC, LCC-64 |
| 文件頁數(shù)： | 10/51頁 |
| 文件大?。?/td> | 227K |
| 代理商： | TLC320AD90CFN |
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2–5
2.2.3
Frame Contents
The SDATA_OUT frame contents are listed in Table 2–2.
Table 2–2. SDATA_OUT Frame Contents (Driven by Audio Controller)
SLO
T
SLOT NAME
BIT
POSITION
NAME
DESCRIPTION
15
Valid Frame
0: Indicates no valid data is in this frame
1: There is at least one TDM slot containing valid data in
the frame.
0
TAG
14
Slot 1 Valid
0: Indicates no data is available in the first time slot of the
data phase. Slot one must be zero-padded.
1: Valid data is available in the first time slot.
13–3
Slot x Valid
0: No valid data is in slot x of the data phase. The
corresponding slot must be zero-padded.
1: Valid data is in slot x
2–0
Zero Pad
Reserved. Must be zeroes.
19
Read/Write
0: Write to the addressed register
1: Read from the addressed register
1
Command Address
18–12
Register
Index
These seven bits are used to access the control registers.
Only the even numbers are used. A total of 64 registers
are defined. Odd numbered register accesses map to the
preceding even boundary.
11–0
Zero Pad
Reserved. Must be zeroes.
2
Command Data
19–4
Register
Data
If the current command operation is a write (see bit 19 of
slot one) then these bits contain the data to be written.
These bits must be zero-padded if the current operation
is a read.
3–0
Zero Pad
Reserved. Must be zeroes.
3
PCM Left Playback
19–4
PCM Data
16-bit audio data. If the resolution is less than 16 bits, then
the data must be right-justified and the LSBs must be
zero-padded.
3–0
Zero Pad
These bits must be zeroes.
4
PCM Right
Playback
19–4
PCM Data
16-bit audio data. If the resolution is less than 16 bits, then
the data must be right-justified and the LSBs must be
zero-padded.
y
3–0
Zero Pad
These bits must be zeroes.
5–12
Reserved
Zero Pad
Reserved. These bits must be zeroes. Note that slot five
is the optional modem line codec.
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